Digital Systems Design VHDL

Learn Digital Systems Design VHDL the exam way—clear concepts, worked examples, and 128 focused lessons in electronics engineering.

Instructor: DAKALA SREENIVASULU

Last updated Aug 2026 en

3 learners enrolled

all-levels

This course includes

— on-demand video
Access on mobile & desktop
Full lifetime access
Certificate of completion

Course content

6 sections · 128 lectures

LEC 01: Introduction to VHDL-Entity Declaration Preview
LEC 02: VHDL Architecture Declaration
LEC 03: Behavioral model of VHDL code
LEC 04: Dataflow model of VHDL code
LEC 05: Structural model of VHDL code
LEC 06: Configuration and Package Declaration
LEC 07: Identifiers in VHDL
LEC 08: Data objects in VHDL_Part 1
LEC 09: Data objects in VHDL_Part 2
LEC 10: Data types_Part 1
LEC 11: Data types_Part 2
LEC 12: Operators in VHDL
LEC 13: Process statement_Part 1
LEC 14: Process statement_Part 2
LEC 15: Concurrent signal assignment statement
LEC 16: Conditional and selected signal assignment statements
LEC 17: Component declaration and instantiation
LEC 18: Differences between VHDL and Verilog codes
LEC 19: STD_LOGIC data types in VHDL
LEC 20: Packages in VHDL

LEC 21: Introduction to Verilog Preview
LEC 22: Gate Level Modeling
LEC 23: Data flow and Behavioral modelling of verilog
LEC 24: Data types
LEC 25: Data Operators_Part 1
LEC 26: Data Operators_Part 2
LEC 27: Data Operators_Part 3
LEC 28: Data Operators_Part 4
LEC 29: Module Statement
LEC 30: If-else in Verilog
LEC 31: Wait, case and Null statement
LEC 32: Loop statements
LEC 33: Comparison of VHDL and Verilog languages

LEC 34: Sub-programs Preview
LEC 35: Parallel binary adder
LEC 36: VHDL code for parallel binary adder
LEC 37: Binary adder and subtractor
LEC 38: Carry look ahead adder_Part 1
LEC 39: Carry look ahead adder_Part 2
LEC 40: VHDL code for carry look ahead adder
LEC 41: BCD adder
LEC 42: VHDL code for BCD Adder
LEC 43: Multiplexer
LEC 44: VHDL code 2x1 mux in dataflow model and behavioral model
LEC 45: 4X1 multiplexer VHDL code in dataflow model
LEC 46: Demultiplexer and its dataflow VHDL code
LEC 47: Demultiplexer structural and behavioural VHDL code
LEC 48: Digital Comparator_Part 1
LEC 49: Digital Comparator_Part 2
LEC 50: 4-bit and 8-bit comparator
LEC 51: Decoder
LEC 52: Decoder VHDL code dataflow and behavioural
LEC 53: 2 to 4 Decoder structural VHDL code
LEC 54: 3 to 8 Decoder
LEC 55: 3 to 8 Decoder VHDL code
LEC 56: 3 to 8 Decoder behavioural VHDL code
LEC 57: 74x139 dual 2 to 4 decoder
LEC 58: 3 to 8 Decoder using two 2 to 4 decoders
LEC 59: 3 to 8 Decoder IC_74X138
LEC 60: Encoder
LEC 61: Encoder VHDL code
LEC 62: 8x3 Encoder
LEC 63: 8x3 Encoder VHDL code
LEC 64: Priority Encoder
LEC 65: Priority Encoder VHDL code_Part 1
LEC 66: Priority Encoder VHDL code_Part 2
LEC 67: 8x3 Priority Encoder
LEC 68: 8x3 Priority Encoder VHDL code_Part 1
LEC 69: 8x3 Priority Encoder VHDL code_Part 2
LEC 70: Arithmetic and Logic Unit_Part 1
LEC 71: Arithmetic and Logic Unit_Part 2
LEC 72: Arithmetic and Logic Unit_VHDL code
LEC 73: Parity circuits
LEC 74: Parity circuits_VHDL code

LEC 75: Sequential logic circuits_Latches Preview
LEC 76: SR Flip flop
LEC 77: SR Flip flop_Behavioral model
LEC 78: JK Flip flop
LEC 79: JK Flip flop VHDL code
LEC 80: T Flip flop
LEC 81: T Flip flop VHDL code
LEC 82: D Flipflop
LEC 83: D Flipflop_VHDL code
LEC 84: Registers_SISO
LEC 85: Registers_SISO_VHDL_Structural
LEC 86: Registers_SISO_VHDL_Behavioral
LEC 87: Registers_SIPO_VHDL code
LEC 88: Registers_PIPO_VHDL code
LEC 89: Registers_PISO
LEC 90: Registers_PISO_VHDL code
LEC 91: Universal shift register_IC74LS194
LEC 92: Universal shift register_IC74LS194 -VHDL code
LEC 93: Counters
LEC 94: Ring Counters
LEC 95: Ring Counters_VHDL code
LEC 96: Johnson Counter
LEC 97: Johnson Counter__VHDL code
LEC 98: Design of N-bit synchronous counter
LEC 99: Design of Mod-16 synchronous counter using T FF
LEC 100: VHDL code for mod 8 counter
LEC 101: IC7493 counter
LEC 102: IC7493 counter__VHDL code
LEC 103: Decade counter IC7490 with VHDL code

LEC 104: Combinational logic circuits with MOS devices Preview
LEC 105: CMOS inverter and 2 input NOR gate
LEC 106: Generalised NOR structure with multiple inputs
LEC 107: Transient analysis of 2 input NOR gate
LEC 108: Generalised NMOS NAND gate
LEC 109: Transient analysis of NMOS NAND gate
LEC 110: CMOS 2 input NAND gate
LEC 111: CMOS 2 input NOR gate
LEC 112: Complex logic circuit
LEC 113: CMOS Complex logic circuit
LEC 114: CMOS AOI logic circuit
LEC 115: CMOS OAI logic circuit
LEC 116: Pseudo NMOS logic gate
LEC 117: CMOS transmission gates
LEC 118: CMOS transmission gates_DC analysis_Part 1
LEC 119: CMOS transmission gates_DC analysis-part 2
LEC 120: Pass transistor logic

LEC 121: Sequential MOS Logic circuit Preview
LEC 122: Behaviour of Bistable elements
LEC 123: SR Latch using NOR gates
LEC 124: SR Latch using NAND gates
LEC 125: Clocked SR latch
LEC 126: Clocked JK latch
LEC 127: D latch implementation
LEC 128: Basic principles of pass transistor circuits

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Description

Digital Systems Design VHDL is an exam-focused electronics engineering programme designed for ECE / EEE learners building circuit and digital fundamentals for exams (all levels). Lessons are paced for semester revision and competitive practice, with clear explanations you can replay anytime.

You will build device and system intuition for Digital Systems Design VHDL, linking theory to typical university numericals and design questions. Syllabus highlights include Introduction to VHDL Programming Language, Introduction to Verilog Programming Language, VHDL Programming on Combinational Logic Design, VHDL Programming on Sequential Logic Design, Combinational Logic Circuits with MOS Devices, and Sequential Logic Circuits with MOS Devices. Across 128 lessons, you will move from foundations to problem-solving patterns that show up in university papers and placement tests.

Taught by DAKALA SREENIVASULU, this course keeps theory short and practice heavy—so you can revise faster, spot examiner cues, and build confidence before mocks and finals.