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VLSI

Learn VLSI the exam way—clear concepts, worked examples, and 87 focused lessons in electronics engineering.

Instructor: DAKALA SREENIVASULU
Last updated Aug 2026 en
25 learners enrolled
all-levels

This course includes

  • — on-demand video
  • Access on mobile & desktop
  • Full lifetime access
  • Certificate of completion

Course content

9 sections · 87 lectures

  • Lec 01: Introduction to VLSI and VLSI design flow Preview
  • Lec 02: Moore's law and IC evolution
  • Lec 03: MOS transistor structure and modes of operation
  • Lec 04: Characteristics of enhancement mode NMOS transistor

  • Lec 05: Steps for MOS transistor fabrication Preview
  • Lec 06: NMOS fabrication steps
  • Lec 07: PMOS fabrication steps
  • Lec 08: CMOS N-Well fabrication
  • Lec 09: CMOS P-Well fabrication
  • Lec 10: Twin-tub process

  • Lec 11: Ids versus Vds derivation_Part1 Preview
  • Lec 12: Ids versus Vds derivation_Part2
  • Lec 13: Aspects of MOS transistor threshold voltage
  • Lec 14: Transconductance and output conductance
  • Lec 15: Figure of merit and pass transistor

  • Lec 16: nMOS inverter Preview
  • Lec 17: Alternate forms of pull ups
  • Lec 18: CMOS inverter
  • Lec 19: Pull up to pull down ratio of nmos inverter driven by another nmos inverter
  • Lec 20: Pull up to pull down ratio for nmos inverter driven through one or more pass transistors
  • Lec 21: Bicmos inverter
  • Lec 22: Difference between CMOS and Bipolar technologies
  • Lec 23: Latch up in CMOS circuits

  • Lec 24: MOS layers for stick diagrams Preview
  • Lec 25: CMOS circuit realizations
  • Lec 26: Rules to draw the Stick diagrams
  • Lec 27: Stick diagram of CMOS inverter
  • Lec 28: Stick diagram of CMOS NAND GATE
  • Lec 29: Stick diagram of CMOS NOR GATE
  • Lec 30: Stick diagram of CMOS logic functions
  • Lec 31: MOS Layout layers
  • Lec 32: Lambda based design rules for Mask layout
  • Lec 33: Layout diagram for CMOS inverter
  • Lec 34: Layout diagram for CMOS 2-input NAND and NOR gates
  • Lec 35: Layout diagram for CMOS logic functions

  • Lec 36: Sheet resistance concept Preview
  • Lec 37: Sheet Resistance concept applied to MOS transistors and Inverters
  • Lec 38: Sheet Resistance concept applied to CMOS Inverter
  • Lec 39: Area capacitance and Standard unit of capacitance
  • Lec 40: Some area capacitance calculations
  • Lec 41: Delay time
  • Lec 42: Inverter delays
  • Lec 43: A More Formal Estimation of CMOS Inverter Delay
  • Lec 44: Propagation delay
  • Lec 45: Wiring capacitances
  • Lec 46: Choice of layers
  • Lec 47: Scaling models and scaling factors
  • Lec 48: Scaling models and scaling factors
  • Lec 49: Limitations on scaling_Part1
  • Lec 50: Limitations on scaling_Part2
  • Lec 52: Limits on logic levels and current density
  • Lec 53: Switch logic
  • Lec 54: Gate logic
  • Lec 55: Pseudo nMOS logic
  • Lec 56: Dynamic CMOS logic
  • Lec 57: Clocked CMOS logic
  • Lec 58: Driving large capacitance_Part1
  • Lec 59: Driving large capacitance_Part2
  • Lec 60: Driving large capacitance_Part3

  • Lec 61: Regions of operations of MOS transistors Preview
  • Lec 62: Common source stage with resistive load
  • Lec 63: Common source stage with diode connected load
  • Lec 64: Common source amplifer analysis without source resistor
  • Lec 65: Common source amplifer analysis with source resistor
  • Lec 66: Common drain amplifier
  • Lec 67: Common gate amplifer
  • Lec 68: MOS device models_Part1
  • Lec 69: MOS device models_Part2
  • Lec 70: Body bias effect in MOS transistor
  • Lec 71: Current sources and sinks_Part1
  • Lec 72: Current sources and sinks_Part2
  • Lec 73: Current sources and sinks_Part3

  • Lec 74: FPGA design flow Preview
  • Lec 75: Basic architecture of FPGA_Part1
  • Lec 76: Basic architecture of FPGA_Part2
  • Lec 77: FPGA technologies_SRAM technology
  • Lec 78: FPGA technologies_Antifuse technology
  • Lec 79: EPROM OR EEPROM technology in FPGA
  • Lec 80: FPGA families_Part1
  • Lec 81: FPGA families_part-2
  • Lec 82: FPGA families_part-3

  • Lec 83: Giga scale dilemma Preview
  • Lec 84: Short channel effects_Part1
  • Lec 85: Short channel effects_Part2
  • Lec 86: High-K dielectric
  • Lec 87: FinFET technology_Part1
  • Lec 88: FinFET technology_Part2

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Description

VLSI is an exam-focused electronics engineering programme designed for ECE / EEE learners building circuit and digital fundamentals for exams (all levels). Lessons are paced for semester revision and competitive practice, with clear explanations you can replay anytime.

You will build device and system intuition for VLSI, linking theory to typical university numericals and design questions. Syllabus highlights include Introduction to VLSI, Fabrication of MOS transistors, Ids vs Vds & other parameters, Inverters & Pull up to pull down ratios, Stick and layout diagrams, and Basic circuit concepts. Across 87 lessons, you will move from foundations to problem-solving patterns that show up in university papers and placement tests.

Taught by DAKALA SREENIVASULU, this course keeps theory short and practice heavy—so you can revise faster, spot examiner cues, and build confidence before mocks and finals.

Instructor

DAKALA SREENIVASULU

DAKALA SREENIVASULU

Course director · Semester exams

Faculty lead for Education4U exam-focused programmes across aptitude, reasoning, computer science, electrical and electronics.

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